1. Field of the Invention
The present invention relates to a driving circuit and a driving method of an active matrix display device in which two adjacent pixels share one signal line, and to an active matrix display device using such a driving circuit.
2. Description of the Related Art
In recent years, an active matrix type display device using a thin-film transistor (TFT) as a switching element has been developed.
The display device includes a scanning line driving circuit (gate driver) which generates scanning signals in order to scan, in turn by row, a plurality of pixels arranged in a matrix form. The gate driver operates at an operation frequency lower than that of a source driver (signal line driving circuit) which supplies video signals to each of the pixels. Therefore, even if the gate driver is formed at the same time in the same process as the process to form TFTs corresponding to each of the pixels, the gate driver can satisfy its specification.
Each pixel of the display device has a pixel electrode connected to a TFT, and a common electrode (common to all of the pixels) to which a common voltage Vcom is applied. In the active matrix type display device, to prevent deterioration of liquid crystals caused by sustained application of an electric field in one direction, inversion driving to invert polarities of a video signal Vsig from the source driver against the common voltage Vcom for each frame, line or dot has been performed generally.
Meanwhile, in mounting the display device, the gate driver and the source driver are disposed around a display panel (display screen), which has a large number of pixels disposed thereon. Wiring lines to electrically connect scanning lines (gate lines), and signal lines (source lines) on the display screen to the gate driver and the source driver are routed around the outside the display screen. At this time, it is strongly desired to make a routing area of the wiring lines smaller, that is, to achieve a reduction in area other than the display panel (i.e., to narrow the picture frame) from a point of view of miniaturizing information equipment having an active matrix display device built-in.
Therefore, in particular, a configuration of pixel wiring lines with half the number of source lines has been developed because the area occupied by the source lines can be made smaller, in order to narrow the picture frames of the display panel in the vertical direction (e.g., as shown in FIG. 5 of Jpn. Pat. Appln. KOKAI Publication No. 2004-185006).
FIG. 19 is a schematic view of an example of pixel wiring lines on a display screen to achieve such a narrowed picture frame. This example shares one source line with two adjacent pixels 200. In this case, TFTs 202 of the two adjacent pixels 200 (in the same row) are connected to respective different gate lines. In FIG. 19, for example, the TFT 202 of the pixel 200 in red (R) at the upper left is connected to a gate line G1 and a source line S1, and the TFT 202 of the neighboring pixel 200 in green (G) to the right is connected to a gate line G2 and the source line S1.
FIG. 20 illustrates a timing chart consisting of the output order of combinations of video signals Vsigs based on the information to be output on a plurality of source lines S1, S2, S3, . . . , and to be displayed, and of the selection order of a plurality of gate lines G1, G2, G3, . . . , in such pixel wire connection lines. As shown in FIG. 20, since the number of the gate lines G1, G2, G3, . . . , is twice of the number of rows of pixels, in the plurality of gate lines G1, G2, G3, one gate line will be selected (will become an H signal) for each half horizontal period (½ H) in accordance with the selection order. The combination of each video signal Vsig to be written in pixels 200 corresponding to the selected gate line is output at one time to a plurality of source lines S1, S2, S3, . . . , during a half horizontal period. For instance, during a half horizontal period in which the gate line G1 is selected, combination “S-1” of video signals Vsigs is output to the plurality of source lines S1, S2, S3, . . . , and in a half horizontal period in which the next gate line G2 is selected, combination “S-2” of video signals Vsigs is output to the plurality of source lines S1, S2, S3, . . . .
FIG. 21 illustrates the writing order of the video signals Vsigs in pixels 200. Since the writing of the video signals Vsigs in pixels 200 is executed in accordance with the arrangement order of the gate lines as shown in FIG. 20, the writing order is as shown in FIG. 21.
In the structure of the pixel wiring lines described above in which the number of the source lines is reduced by half, some adjacent columns of pixels have a source line therebetween, and other adjacent columns of pixels do not have a source line therebetween. As illustrated in the equivalent circuit of FIG. 22, at the points without source lines between pixels, there is parasitic capacitance between the pixels that is larger than at points where a source line is provided between adjacent pixels. Among pixels having inter-pixel parasitic capacitance 204, voltage leakages occur, and as a result the electrical potential at the pixel 200 written first varies under the influence of the voltage at the pixel 200 written later. The variation in voltage appears as display unevenness on the screen. Since the order of writing is fixed as depicted in FIG. 21, the display unevenness caused by the leakage always occurs at the same points.
FIG. 23 is a view illustrating an example of the display unevenness. FIG. 23 illustrates the display unevenness only of the G pixels 200 so as to make the example clearly understandable. Here, the scanning order of the gate lines is expressed as G1, G2, G3, . . . , G8. At the pixels 200 of other colors which are depicted in a ground color black in FIG. 23, the electrical potential of the pixels 200 written first varies in a similar manner (described in detail later).
FIG. 24 shows configurations of each pixel when the display panel is a TFT liquid crystal display (LCD). Each pixel 200 is configured such that a liquid crystal (not shown) is held between the common electrode to which the common voltage Vcom is to be applied (not shown) and the pixel electrode connected to a source line through a TFT 202 which is also connected with a gate line. Holding an electric charge at a liquid crystal capacitor Clc over a field period (frame period in the case of a non-interlace system) achieves the corresponding display. As a countermeasure against current leakage through the capacitor Clc and the TFT, an auxiliary capacitor Cs is disposed in parallel with the capacitor Clc.
FIG. 25A is a scanning timing chart of gate lines G1-G4 by the gate driver. FIG. 25B is a view illustrating pixel electrical potential waveforms of a pixel F in green connected, for example, to the source line S3 in FIG. 22 to be written earlier (pixel “G-first”), and of a pixel L in red connected, for example, to the source line S2 in FIG. 22 to be written later (pixel “R-later”) when horizontal line inversion driving, which reverses the polarity of a common voltage Vcom every half horizontal period (½ H), is performed.
Hereinafter, the case of a liquid crystal display device in a normally white mode that reduces a transmission factor (becomes dark) as the voltage applied to the pixel becomes larger will be described. FIG. 25B shows the case in which the amplitude of the common voltage Vcom is set to 5.0V, the voltage to write the pixel F (G-first) (video signal Vsig) is set to 2.0V against the common voltage Vcom (intermediate tone), and the voltage to write the pixel L (R-later) (video signal Vsig) is set to 4.0V against the common voltage Vcom (black, dark). Since the influence of drawing voltage (field through voltage) ΔV generated when the TFT 202 is switched from on to off can be cancelled through adjustment of the common voltage Vcom (shift Vcom downward by ΔV), the influence is not illustrated at the waveform in FIG. 25B (the same applies to figures of other pixel electrical potential waveforms described later).
As shown in FIG. 25A, if the period to write the video signals in the pixels of one row on the display screen is set as one horizontal period, two gate lines are selected sequentially in the one horizontal period. That is, if the period in which one gate line is selected is set to one scanning period, the one horizontal period is equivalent to two scanning periods (one scanning period is equivalent to the half horizontal period mentioned above). The two gate lines to be selected in the one horizontal period are switched sequentially for every horizontal period in each field. At this moment, as shown in FIG. 25B, the TFTs 202 connected to the selected gate line are turned on, and the video signals Vsigs applied from the source lines are written to the corresponding pixels 200. Accordingly, the write timing of the pixel F (G-first) becomes WG, and the write timing of pixel L (R-later) becomes WR in FIG. 25B. The pixel electrical potential written at the write timing is maintained until that pixel is re-written in the next field.
FIG. 25B illustrates pixel electrical potential waveforms in an ideal state when the inter-pixel parasitic capacitance 204 is “0”. However, as mentioned above, the inconvenience of the occurrence of the capacitance 204 is generated at the point between pixels with no source line. FIG. 26A is a view illustrating the pixel electrical potential waveforms under the same voltage conditions as those of FIG. 25B with the capacitance 204 taken into consideration. FIG. 26B is a view illustrating the pixel electrical potential waveform in the case in which the amplitude of the common voltage Vcom is set to 5.0V, the write voltage of the pixel F (G-first) is set to 2.0V against the common voltage Vcom, and the write voltage of the pixel L (R-later) is set to 1.0V (white, bright), when the capacitance 204 is taken into account.
As shown in FIG. 26A and FIG. 26B, at the pixel F (G-first), the pixel electrical potential written by selecting the gate line G1 shifts to the direction going away from the common voltage Vcom (direction getting dark) by an electrical potential variation Vc in writing the pixel L (R-later) by selecting the gate line G2. The height of the variation Vc is expressed by the following equation (Eq.) (1):Vc=(Vsig(Fn-1)+Vsig(Fn))×Cpp/(Cs+Clc+Cpp)×α  (1)
In Eq. (1), “Vsig(Fn)” is the write voltage of the pixel L (R-later) in a current field, and “Vsig(Fn-1)” is the write voltage of the pixel L (R-later) in the preceding field. Therefore, in the case of FIG. 26A, “Vsig(Fn-1)+Vsig(Fn)=8.0V” is satisfied, and in the case of FIG. 26B, “Vsig(Fn-1)+Vsig(Fn)=2.0V” is satisfied. Cpp is a capacitance value of the parasitic capacitance 204, Cs is a capacitance value of the auxiliary capacitance Cs, Clc is a capacitance value of the liquid crystal capacitance Clc, and a is a proportional factor whose value is determined in accordance with a panel structure, etc.
As described above, the larger the value of “Vsig(Fn-1)+Vsig(Fn)” is, the larger the value Vc of electrical potential variation becomes, and it does not depend on the magnitude of the amplitude of the common voltage Vcom.
The description above has described the case of the horizontal line inversion driving which differs in polarity of the common voltage Vcom (polarity of a voltage to be applied to a liquid crystal) among pixels adjacent to one another in the direction along the source line. That is, the description is the case in which, for instance, in FIG. 21, the polarity of the common voltage Vcom is inverted for the pixels connected to the gate line G3 or G4 with respect to the pixels connected to the gate line G1 or G2, and is similarly inverted for the pixels connected to the gate line G5 or G6 with respect to the pixels connected to the gate line G3 or G4, and is inverted for the pixels connected to the gate line G7 or G8 with respect to the pixels connected to the gate line G5 or G6.
To perform the polarity inversion of the common electrode Vcom, a driving method referred to as dot inversion driving is known. In this driving method, the polarity of the common voltage Vcom differs between pixels adjacent to each other in the direction along the source line and between pixels adjacent to each other in the direction along the gate line. In this driving method, so that the polarities of the common voltages Vcoms among pixels adjacent to each other from right to left or up-and-down invert with respect to each other, the polarity of the common voltage Vcom is inverted between the gate line G1 and the gate line G2, between the gate line G3 and the gate line G4, between the gate line G5 and the gate line G6, and between the gate line G7 and the gate line G8.
In any case of the horizontal line inversion driving and the dot inversion driving, the polarities of the common voltages Vcoms at the respective pixels are inverted in each field.
FIGS. 27A and 27B show the cases of performing such dot inversion driving. Here, FIG. 27A illustrates the pixel electrical potential waveforms in the case in which the amplitude of the common voltage Vcom is set to 5.0V, the write voltage of the pixel F (G-first) is set to 2.0V (intermediate tone) against the common voltage Vcom, and the write voltage of the pixel L (R-later) is set to 4.0V (black) against the common voltage Vcom, taking the inter-pixel parasitic capacitance 204 into account. FIG. 27B illustrates the pixel electrical potential waveforms in the case in which the amplitude of the common voltage Vcom is set to 5.0V, the write voltage of the pixel F (G-first) is set to 2.0V against the common voltage Vcom, and the write voltage of the pixel L (R-later) is set to 1.0V (white) against the common voltage Vcom, taking the inter-pixel parasitic capacitance 204 into account.
As shown in FIGS. 27A and 27B, also when performing the dot inversion driving, in the same way as when performing the horizontal line inversion driving, at the pixel F of G-first, in writing the pixel L of R-later by selecting the gate line G2, the pixel electrical potential written by selecting the gate line G1, shifts by the variation Vc.
Also in such a case, the larger the value of “Vsig(Fn-1)+Vsig(Fn)” is, the larger the value Vc of the electrical potential variation becomes, and the variation Vc does not depend on the amplitude of the common voltage Vcom as in the case of the horizontal line inversion driving.
In the horizontal line inversion driving, the potential variation occurs in such a manner as to increase the potential difference between the common voltage Vcom and the write voltage. In the dot inversion driving, in contrast, the potential variation occurs in such a manner as to decrease the potential difference between the common voltage Vcom and the write voltage.
In the normally white mode, wherein “white” is displayed when no voltage is applied and “black” is displayed when voltage is applied, the variations of Vc as described above result in making the pixel G-first darker than intended in the case of the horizontal line inversion driving. In the case of the dot inversion driving, the variations described above result in making the pixel G-first brighter than intended. On the other hand, G pixels written later (“G-later”) have a normal voltage for the pixel electrical potential. As a result, a display like a G raster results in displays of alternate bright and dark lines in a longitudinal direction also in both horizontal line inversion driving and dot inversion driving.
Similar variations of the variation Vc also occur at the pixel R-first and at the pixel B-first.
The situation described above is not limited in the case of a strip arrangement of the pixels 200, and also applies to the case of a delta arrangement.
The method disclosed by the foregoing Jpn. Pat. Appln. KOKAI Publication No. 2004-185006 cannot deal with the problem of display unevenness due to the electrical potential variations generated at the previously written pixels caused by such inter-pixel parasitic capacitance 204.